Signal integrity is not an afterthought. Here is how we think about layout from day one.
Signal integrity is not something you bolt on at the end — it is baked into every trace, every via, every layer stack.
When you are designing a PCB for high-speed signals, the laws of physics do not care about your deadline. Every millimetre of trace is a transmission line. Every via is an impedance discontinuity. Ignore these realities early, and you will pay for it in respins.
Start With the Stack-Up
Before placing a single component, we define the layer stack-up. The number of layers, their thickness, the dielectric constant of the material — all of these determine the characteristic impedance of your traces.
- Define controlled impedance requirements upfront with your PCB fabricator.
- Use a solid reference plane directly below every high-speed signal layer.
- Minimise split planes — return currents follow the path of least impedance, not least resistance.
Routing Rules We Never Break
Differential pairs must be routed together from the very first segment. Length-matching is critical but phase matching matters more.
| Signal Type | Trace Width | Key Constraint |
|---|---|---|
| USB 3.0 differential | 0.1 mm / 0.2 mm gap | Match within 0.1 mm |
| DDR4 data | 0.1 mm | Match within byte lane ±5 ps |
| RF / microwave | Calculated per stack-up | Maintain 50 Ω ±10% |
| LVDS | 0.1 mm / 0.18 mm gap | No layer changes mid-route |
Simulation Before Fabrication
We run pre-layout channel simulation to validate the architecture and post-layout extraction to catch any violations before sending to the fab.
